1. Field of the Invention
This disclosure generally relates to structures and methods for forming good electrical connections between an integrated circuit (IC) chip and a chip carrier of a flip chip package. More particularly, addition of one of: tensile layers and a compressive layer, to selected surfaces of IC chips in a wafer prior to solder bump re-heating, may reduce or modulate warpage of the IC chip and enhance wetting of opposing solder surfaces of solder bumps on the IC chip and solder formed on flip chip (FC) attaches of a chip carrier in a flip chip package.
2. Description of Related Art
The semiconductor marketplace continues to demand smaller devices, which require greater connectivity densities for packaging design. The increased functionality of smaller semiconductor devices requires an increased number of signal, power, and ground connections, and a corresponding decrease in connection pitch is required to maintain reasonable chip size. The combination of these requirements results in greater complexity of semiconductor packaging design.
Referring to FIG. 1, the packaging design requirement is especially critical in flip chip packages, where demand for a greater density of connections must coexist with good electrical and reliability performance. When compared to other packaging technologies, flip chip packaging significantly increases the number of signal, power and ground connections of the integrated circuit (IC) chip that are connected to the chip carrier through solder bumps or controlled collapse chip connections (C4s). Following solder re-heating, chip-join and cool-down, the solder bumps of the IC chip and the solder of the flip chip (FC) attaches of the chip carrier form electrical and mechanical connections between the IC chip and the chip carrier of the flip chip package. In turn, the FC attaches electrically connect through various pathways of the chip carrier to, for example, a ball grid array or land grid array that connect to a system board.
Typically, the process steps for a flip chip package include: creating IC chips on a silicon wafer; forming underbumps on a front side surface of the IC chip, i.e., above the silicon layers of the IC chip; depositing solder bumps or C4 connections on each of the underbumps; singulating or cutting the IC chips from the silicon wafer; “flipping” and positioning each IC chip, so that the solder bumps of the IC chip oppose the solder layers formed on the FC attaches of a chip carrier; and re-heating the solder bumps and the solder layers formed on the FC attaches to effect chip-join. Optionally, an electrically insulating underfill is subsequently introduced between the overlying IC chip and the underlying chip carrier, to prevent mechanical flexion of the solder connections between the IC chip and the chip carrier of the flip chip package.
Joining of the IC chip to the chip carrier requires re-heating of the solder bumps and the solder layers of the FC attaches, so as to “wet” the opposing solder surfaces of the solder bumps and the solder layers of the FC attaches. This wetting allows the miscible solders of the opposing solder surfaces to form an effective electrical connection upon subsequent cooling.
During heating, both the IC chip and the chip carrier can warp because of mismatches between the coefficients of thermal expansion (CTE) of their constituent layers. Relative to room temperature, as shown in the cross section of FIG. 2, the IC chip 220, at a temperature of 245° C., shows a slight negative warp, i.e., the IC chip's center is lower than the corners; whereas, the chip carrier 240 shows a positive warp, i.e., the chip carrier's center is higher than its corners. The relatively more compliant chip carrier typically warps to a greater extent than does the IC chip. Warping represents a change in height of sub-areas across the surface area of either the IC chip or the chip carrier relative to a reference plane at room temperature and at an elevated temperature. The extent of warping of the IC chip and the chip carrier is proportional to a radial distance from a centrally located neutral point, i.e., DNP, of each of the IC chip and the chip carrier. Hence, the relative movement between the opposing solders on the IC chip and the chip carrier is greatest at the edges of the IC chip. At peak elevated temperatures, e.g., 250° C., the solder of the solder bumps, along the edges of the IC chip, and the solder of the opposing FC attaches are physically separated and contact is impossible.
During subsequent cooling, the respective solders of the physically separated solder bumps of the IC chip and the opposing FC attaches of the chip carrier can solidify; thus, precluding any “wetting” of the two opposing solders to form a high quality electrical solder connection. Upon subsequent cooling to room temperature, the IC chip and the chip carrier can flatten; thus, providing physical contact (possibly, with mechanical deformation) at interfaces formed between the previously solidified solder bumps of the IC chip and the previously solidified solder layers of the FC attaches, i.e., a non-wet interface. However, the quality of the electrical contacts between these previously solidified solder contacts is not as good as that of “wetted” contacts between the two opposing miscible solders of the heated solder bumps of the IC chip and the heated solder layers of the FC attaches.
There remains a need to reliably form a “wet” contact between solder bumps of the integrated circuit (IC) chip and the solder layers of the opposing flip chip (FC) attaches of the chip carrier at an elevated temperature, where warping of the IC chip and the chip carrier may occur in a flip chip package.